4-129 cdp1883, cdp1883c cmos 7-bit latch and decoder memory interfaces march 1997 features ? performs memory address latch and decoder func- tions multiplexed or non-multiplexed ? interfaces directly with the cdp1800-series micropro- cessors ? allows decoding for systems up to 32k bytes description the cdp1883 is a cmos 7-bit memory latch and decoder circuit intended for use in cdp1800-series microprocessor systems. it can serve as a direct interface between the multi- plexed address bus of this system and up to four 8k x 8-bit memories to implement a 32k-byte memory system. with four 4k x 8-bit memories, a 16k-byte system can be decoded. the device is also compatible with non-multiplexed address bus microprocessors. by connecting the clock input to v dd , the latches are in the data-following mode and the decoded outputs can be used in general-purpose memory-system applications. the CDP1833 is compatible with cdp1800-series micropro- cessors operating at maximum clock frequency. the cdp1883 and cdp1883c are functionally identical. they differ in that the cdp1883 has a recommended operat- ing voltage range of 4v to 10.5v and the c version has a recommended operating voltage range of 4v to 6.5v. the cdp1883 and cdp1883c are supplied in 20 lead dual- in-line plastic packages (e suf?x). pinout cdp1883, cdp1883c (pdip) top view ordering information 5v 10v temp. range package pkg. no. cdp1883ce cdp1883e -40 o c to +85 o c pdip e20.3 11 12 13 14 15 16 17 18 20 19 10 9 8 7 6 5 4 3 2 1 clock ma0 ma1 ma2 ma3 ma4 ma6 ma5 ce v ss v dd a9 a10 a11 a8 a12 cs0 cs1 cs2 cs3 file number 1507.2 caution: these devices are sensitive to electrostatic discharge; follow proper ic handling procedures. http://www.intersil.com or 407-727-9207 | copyright ? intersil corporation 1999
4-130 absolute maximum ratings thermal information dc supply voltage range, (v dd ) (all voltages referenced to v ss terminal) cdp1883 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5v to +11v cdp1883c. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5v to +7v input voltage range, all inputs . . . . . . . . . . . . . -0.5v to v dd +0.5v dc input current, any one input . . . . . . . . . . . . . . . . . . . . . . . . . 10ma thermal resistance (typical) q ja ( o c/w) pdip package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 device dissipation per output transistor t a = full package temperature range . . . . . . . . . . . . . . . 100mw operating temperature range (t a ) package type e . . . . . . . . . . . . . . . . . . . . . . . . . . .-40 o c to +85 o c storage temperature range (t stg ). . . . . . . . . . . .-65 o c to +150 o c lead temperature (during soldering) at distance 1/16 1/32 in. (1.59 0.79mm) from case for 10s max . . . . . . . . . . . . . . . . . . . . . . . . . . . . +265 o c caution: stresses above those listed in the absolute maximum ratings may cause permanent damage to the device. this is a stre ss only rating and opera- tion of the device at these or any other conditions above those indicated in the operation section of this speci?cation is not implied. recommended operating conditions at t a = full package temperature range. for maximum reliability, operating conditions should be selected so that operation is always within the following ranges: parameter symbol cdp1883 cdp1883c units min max min max dc operating voltage range 4 10.5 4 6.5 v input voltage range v ss v dd v ss v dd v static electrical speci?cations at t a = -40 o c to +85 o c, v dd 5 %, except as noted: parameter symbol conditions cdp1883 cdp1883c units v o (v) v in (v) v dd (v) min (note 1) typ max min (note 1) typ max quiescent device current i dd - 0, 5 5 - 1 10 - 5 50 m a - 0, 10 10 - 10 100 - - - m a output low drive (sink) current i ol 0.4 0, 5 5 1.6 3.2 - 1.6 3.2 - ma 0.5 0, 10 10 3.2 6.4 - - - - ma output high drive (source) current i oh 4.6 0, 5 5 -1.15 -2.3 - -1.15 -2.3 - ma 9.5 0, 10 10 -2.3 -4.6 - - - - ma output voltage low-level (note 2) v ol - 0, 5 5 - 0 0.1 - 0 0.1 v - 0, 10 10 - 0 0.1 - - - v output voltage high-level (note 2) v oh - 0, 5 5 4.9 5 - 4.9 5 - v - 0, 10 10 9.9 10 - - - - v input low voltage v il 0.5, 4.5 - 5 - - 1.5 - - 1.5 v 0.5, 9.5 - 10 - - 3 - - - v input high voltage v ih 0.5, 4.5 - 5 3.5 - - 3.5 - - v 0.5, 9.5 - 10 7 - - - - - v input leakage current i in any input 0, 5 5 - - 1- - 1 m a 0, 10 10 - - 2- - - m a operating current (note 3) i dd1 0, 5 0, 5 5 - - 2 - - 2 ma 0, 10 0, 10 10 - - 4 - - - ma cdp1883, cdp1883c
4-131 functional diagram minimum data retention voltage v dr v dd = v dr - 2 2.4 - 2 2.4 v data retention current i dr v dd = 2.4v - 0.01 1 - 0.5 5 m a input capacitance c in - - - - 5 7.5 - 5 7.5 pf output capacitance c out - - - - 10 15 - 10 15 pf notes: 1. typical values are for t a = +25 o c. 2. i ol = i oh = m a 3. operating current measured at 200khz for v dd = 5v and 400khz for v dd = 10v, with outputs open circuit. static electrical speci?cations at t a = -40 o c to +85 o c, v dd 5 %, except as noted: (continued) parameter symbol conditions cdp1883 cdp1883c units v o (v) v in (v) v dd (v) min (note 1) typ max min (note 1) typ max 2 3 4 5 6 7 8 1 20 10 9 11 12 13 14 17 16 15 18 19 d c q d c q d c q d c q d c q q d c q d c q q ma0 ma1 ma2 ma3 ma4 ma5 ma6 clock ce a8 a9 a10 a11 a12 cs0 cs1 cs2 cs3 v dd = v ss = cdp1883, cdp1883c
4-132 signal descriptions/pin functions clock: latch input control - a high on the clock input will allow data to pass through the latch to the output pin. data is latched on the high-to-low transition of the clock input. this pin is connected to tpa in cdp1800-series systems and tied to v dd for other applications. ma0 - ma4: address inputs to the high-byte address latches. ma5 - ma6: high byte address inputs decoded to produce chip selects cs0 - cs3. ce: chip enable input - a low on this pin will enable the chip select decoder. a high on this pin forces cs0, cs1, cs2, and cs3 outputs to a high (false) state. a8 - a12: latched high-byte address outputs. cs0 - cs3: one of four latched and decoded chip select outputs. v dd , v ss : power and ground pins, respectively. application information the cdp1883 and cdp1883c can be interfaced, without external components, with cdp1800-series microprocessor systems. these microprocessors feature a multiplexed address bus and provide an address latch signal (tpa) that is used as the clock input of the cdp1883. see figure 2 and figure 3. this signal is used to latch 7 bits of the high-order address. the lower ?ve high-order address inputs are latched and held to be used with the eight lower-order address inputs to access an 8k x 8-bit memory. the two upper high-order address inputs are latched and decoded for use as chip selects. the latched address and decoding functions of the cdp1883 and cdp1883c allow them to operate with 32k- byte memory systems. in addition, smaller memory systems can be con?gured with 4k x 8-bit or smaller memories, or a mix of memory sizes up to 8k x 8-bit. truth table inputs outputs ce clk ma5 ma6 cs0 cs1 cs2 cs3 01000111 01101011 01011101 01111110 0 0 x x previous state 1xxx1111 truth table inputs outputs ce clk ma0 - 4 a8 - a12 x11 1 x10 0 x 0 x previous state x = dont care dynamic electrical speci?cations t a = -40 o c to +85 o c, v dd 5%, t r , t f = 20ns, v ih = 0.7 v dd , v il = 0.3 v dd , c l = 100pf. see figure 1 parameter v dd (v) cdp1883 cdp1883c units min (note 1) typ (note 2) max min (note 1) typ (note 2) max minimum setup time, memory address to clock t macl 5 - 10 35 - 10 35 ns 10 - 8 25 - - - ns minimum hold time, memory address after clock t clma 5-825-825ns 10 - 8 25 - - - ns minimum clock pulse width t clcl 5 - 50 75 - 50 75 ns 10 - 25 40 - - - ns propagation delay times chip enab le to chip select t cecs 5 - 75 150 - 75 150 ns 10 - 45 100 - - - ns clock to chip select t clcs 5 - 100 175 - 100 175 ns 10 - 65 125 - - - ns cdp1883, cdp1883c
4-133 all intersil semiconductor products are manufactured, assembled and tested under iso9000 quality systems certi?cation. intersil products are sold by description only. intersil corporation reserves the right to make changes in circuit design and/o r speci?cations at any time without notice. accordingly, the reader is cautioned to verify that data sheets are current before placing orders. information furnishe d by intersil is believed to be accurate and reliable. however, no responsibility is assumed by intersil or its subsidiaries for its use; nor for any infringements of p atents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of intersil or its subsidiaries. for information regarding intersil corporation and its products, see web site http://www.intersil.com clock to address t cla 5 - 100 175 - 100 175 ns 10 - 65 125 - - - ns memory address to chip select t macs 5 - 100 175 - 100 175 ns 10 - 75 125 - - - ns memory address to address t maa 5 - 80 125 - 80 125 ns 10 - 40 60 - - - ns notes: 1. typical values are for t a = 25 o c. 2. maximum limits of minimum characteristics are the values above which all devices function. figure 1. cdp1883 timing waveforms dynamic electrical speci?cations t a = -40 o c to +85 o c, v dd 5%, t r , t f = 20ns, v ih = 0.7 v dd , v il = 0.3 v dd , c l = 100pf. see figure 1 (continued) parameter v dd (v) cdp1883 cdp1883c units min (note 1) typ (note 2) max min (note 1) typ (note 2) max valid chip enable (a) chip enable to chip select propagation delay (b) memory address setup and hold time t cecs t cecs t clma t macl t clcl t clcs t cla a8 - a12 cs0, cs1, cs2, cs3 clock ma0 - ma5 cs0, cs1, cs2, cs3 ce t macs t macs t maa t maa cdp1883, cdp1883c
4-134 figure 2. minimum cdp1800-system using the cdp1883 interface with an 8k x 8-bit memory figure 3. 32k-byte rom system using the cdp1883 cdp1883 latch/ decoder a0 - a6 clk cs0 cs1 cs2 cs3 we ce a0 - a7 cdm6264 8k x 8 ce cdp1837c 4k x 8 rom tpa a0 - a7 mrd ceo tpa mrd mwr cdp1800 series cpu w ait clr a8 - a12 address bus data bus oe ram cdp1883 latch/ decoder cs3 cs2 cs1 cs0 clk ce ma0 - ma6 a8 - a12 w ait clr tpa mrd cdp1800 series cpu cdm5364 8k x 8 rom a0 - a7 ce a8 - a12 cdm5364 8k x 8 rom a8 - a12 ce a0 - a7 cdm5364 8k x 8 rom a8 - a12 ce a0 - a7 cdm5364 8k x 8 rom a8 - a12 ce a0 - a7 address bus address bus data bus cdp1883, cdp1883c
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